Question about ADC and power reduction register

hello

i thought adcsra &= ~(1<<aden) deactivates adc , thats before put mcu sleep , works fine. there pradc bit in power reduction register , never understood or does. description is:

quote

writing logic 1 bit shuts down adc. adc must disabled before shut down. analog
comparator cannot use adc input mux when adc shut down.

ok...but thought adcsra &= ~(1<<aden) trick ? why need shut down 2 times ?

 i did tests , figured out there no benefit in sleep mode doing both things. difference in active mode, after zeroing aden bit , writing 1 pradc bit consumes round 30-50µa less. cant tell if dmm fluctuation or actual real power savings.

so pradc , isnt adc shut down aden bit cleared ?

the a/d disabled when aden cleared. pradc bit shuts down more of hardware, including comparator. amount of current savings relatively small (a few percent) when in active mode. makes more of difference in idle mode.

in power down clocks stopped. according datasheet prr register has no effect then.

at 5v got these numbers (atmega328p):

151ua - power down mode, aden = 1, pradc = 0   // adc enabled
151ua - power down mode, aden = 1, pradc = 1   // can't shut down unless disabled first
0.1ua - power down mode, aden = 0, pradc = 0    // adc disabled not shut down
0.1ua - power down mode, aden = 0, pradc = 1    // adc shut down

the resolution of dmm 0.1ua.

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